Freescale Semiconductor MCF5480 - Manual (Page 339)

XL Bus Arbiter
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 10-17
When enabled, the software programmable value in the arbiter master priority register (XARB_PRI) is
used as the priority for the master. When disabled, the master’s priority is determined as follows:
10.3.3.11 Arbiter Master Priority Register (XARB_PRI)
The master n priority bits of the arbiter master priority register are used to set the priority of each master
if the corresponding arbiter master priority enable register bit is enabled. This XARB_PRI register, in
conjunction with the arbiter master priority enable (XARB_PRIEN) register, allows master priorities to be
set, ignoring the hardcoded priority. This register may be written at anytime. The change will become
effective 1 clock after the register is written. Valid values are from 0 to 7, with 0 being the highest priority.
Table 10-14. XARB_PRIEN Field Descriptions
Bits Name Description
31–4 — Reserved, should be cleared.
3 M3 Master 3 Priority Register Enable
2 M2 Master 2 Priority Register Enable
1 — Reserved, should be cleared.
0 M0 Master 0 Priority Register Enable
Table 10-15. Hardcoded Master Priority
Master Priority Description
M7–M4 — Unused
M3 7 PCI Target Interface
M2 7 Multichannel DMA
M1 — Unused
M0 7 ColdFire core
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 Reserved 0 Reserved 0 Reserved 0 Reserved
W
Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 M3 Priority 0 M2 Priority 0 Reserved 0 M0 Priority
W
Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
Reg
Addr
MBAR + 0x0268
Figure 10-15. Arbiter Master Priority Register (XARB_PRI)