2 gpt counter input register (gcirn), Gpt counter input register (gcirn) -5, 2 gpt counter input register (gcir n ) – Freescale Semiconductor MCF5480 User Manual
Page 345
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
11-5
11.3.2
GPT Counter Input Register (GCIRn)
8
IEN
Interrupt enable. Enables interrupt generation to the CPU for all modes (IC, OC, PWM, and Internal
Timer). IEN is not required for watchdog expiration to create a reset.
0 Interrupt disabled
1 Interrupt enabled
7–6
—
Reserved, should be cleared.
5–4
GPIO
GPIO mode type. Simple GPIO functionality that can be used simultaneously with the internal timer
mode. It is not compatible with IC, OC, or PWM modes, because these modes dictate the usage of
the I/O signals.
0X Timer enabled as simple GPIO input on TINn
10 Timer enabled as simple GPIO output, TOUTn=0
11 Timer enabled as simple GPIO output, TOUTn=1 (tri-state if OD=1)
While in GPIO modes, internal timer mode is also available. To prevent undesired timer expiration,
keep the CE bit cleared.
3
—
Reserved, should be cleared.
2–0
TMS
Timer mode select (and module enable).
000 Timer module not enabled. All timer operation is completely disabled. Control and status
registers are still accessible. This mode should be entered when the timer is to be re-configured,.
001 Timer enabled for input capture.
010 Timer enabled for output capture.
011 Timer enabled for PWM.
1XX Timer enabled for simple GPIO. Internal timer modes available. CE bit controls timer counter.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PRE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CNT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x804 (GCIR0), 0x814 (GCIR1), 0x824 (GCIR2), 0x834 (GCIR3)
Figure 11-2. GPT Counter Input Register (GCIRn)
Table 11-2. GMSn Field Descriptions (Continued)
Bits
Name
Description