Freescale Semiconductor MCF5480 - Manual (Page 353)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 13-1
Chapter 13
Interrupt Controller
13.1 Introduction
This section details the functionality for the MCF548x interrupt controller. The general features of the
interrupt controller include:
• 63 interrupt sources, organized as:
— 56 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
• Each of the 63 sources has a unique interrupt control register (ICRn) to define the
software-assigned levels and priorities within the level
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source, plus global mask-all capability
• Support for both hardware and software interrupt acknowledge cycles
• “Wake-up” signal from stop mode
The 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers
on the MCF548x handle the complete set of interrupt sources from all of the modules on the device. This
section describes how the interrupt sources are mapped to the interrupt controller logic, and how interrupts
are serviced.
13.1.1 68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the MCF548x interrupt controller, a brief review of the interrupt
architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once per instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If
the priority level is greater than the SR[I] field at the sample point, the processor suspends normal
instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as
non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and
may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire requires that,
once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer
type and transfer modifier attributes to distinguish this data fetch from a “normal” memory access. The
fetched data provides an index into the exception vector table that contains 256 addresses, each pointing
to the beginning of a specific exception service routine. In particular, vectors 64–255 of the exception
vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for
the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc.
Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are 2 longwords in length and contain 32 bits of vector