Freescale Semiconductor MCF5480 - Manual (Page 355)

Introduction
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 13-3
8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt
source is hardwired to the given level and represents the mid-point of the priority within the level. For the
fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in
the 8-bit interrupt control register (ICRn).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
13.1.1.1.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register to
determine if there are active requests. This is the recognition phase.
13.1.1.1.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit
decoded priority level (IRQ[7:1]) is driven out of the interrupt controller.
13.1.1.1.3 Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates
an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by
the processor and routed to the interrupt controller. Next, the interrupt controller extracts the level being
acknowledged from address bits[4:2], determines the highest priority interrupt request active for that level,
and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is
formed using the following algorithm:
vector_number = 64 + interrupt source number
Recall vector numbers 0—63 are reserved for the ColdFire processor and its internal exceptions. Thus, the
mapping of bit positions to vector numbers that apply are the following:
if interrupt source 1 is active and acknowledged, then vector_number = 65
if interrupt source 2 is active and acknowledged, then vector_number = 66
...
if interrupt source 8 is active and acknowledged, then vector_number = 72
if interrupt source 9 is active and acknowledged, then vector_number = 73
...
if interrupt source 63 is active and acknowledged, then vector_number = 127
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector
number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned, and it is the responsibility of the service routine to handle this error
situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since
the interrupt controller completely services the acknowledge. This means the interrupt source must be