2 interrupt mask register (imrh, imrl), Interrupt mask register (imrh, imrl) -7 – Freescale Semiconductor MCF5480 User Manual
Page 359
Memory Map/Register Descriptions
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
13-7
13.2.1.2
Interrupt Mask Register (IMRH, IMRL)
The IMRH and IMRL registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 = disable the request, 0 = enable the request). The IMR is set to all ones by
reset, disabling all interrupt requests. The IMR can be read and written. A write that sets bit 0 of the IMR
forces the other 63 bits to be set, disabling all interrupt sources and providing a global mask-all capability.
NOTE
If an interrupt source is masked in the interrupt controller mask register
(IMR) or a module’s interrupt mask register while the interrupt mask in the
status register (SR[I]) is set to a value lower than the interrupt’s level, a
spurious interrupt may occur. This situation occurs because by the time the
status register acknowledges the interrupt, it has been masked and the CPU
cannot determine the interrupt source. To avoid this situation for interrupt
sources with levels 1–6, first write a higher level interrupt mask to the status
register before setting the mask in the IMR or the module’s interrupt mask
register. After the mask is set, return the interrupt mask in the status register
to its previous value. Since level 7 interrupts cannot be disabled in the status
register prior to masking, use of the IMR or module interrupt mask registers
to disable level 7 interrupts is not recommended.
Table 13-4. IPRL Field Descriptions
Bits
Name
Description
31–1
INT[31:1]
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRL bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRL samples the signal generated by the interrupting source. The corresponding IPRL bit reflects
the state of the interrupt signal even if the corresponding IMRL bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
INT_MASK[63:48]
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INT_MASK[47:32]
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reg
Addr
MBAR + 0x708
Figure 13-3. Interrupt Mask Register High (IMRH)