1 overview, Overview -2 – Freescale Semiconductor MCF5480 User Manual
Page 374
MCF548x Reference Manual, Rev. 3
15-2
Freescale Semiconductor
Figure 15-1. MCF548
x
GPIO Module Block Diagram
15.1.1
Overview
The MCF548x GPIO module controls the configuration and use for the following external GPIO ports
(register types in parentheses):
•
ColdFire bus (FlexBus) accesses (FBCTL, FBCS)
DACK[1:0] / PDMA[3:2]
FBCS[5:1] / PFBCS[5:1]
BWE[3:0] / PFBCTL[7:4]
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PSC3CTS / PPSC3PSC27
DSPISCK / PDSPI2
PORT
FBCTL
FBCS
DMA
FEC0H
FEC0L
FEC1H
FEC1L
PCIBG
PCIBR
PSC3PSC2
PSC1PSC0
DSPI
OE / PFBCTL3
TA / PFBCTL1
R/W / PFBCTL2
ALE / PFBCTL0
DREQ[1:0] / PDMA[1:0]
FEC0TXCLK / PFEC0H7
FEC0TXEN / PFEC0H6
FEC0TXD0 / PFEC0H5
FEC0COL / PFEC0H4
FEC0RXCLK / PFEC0H3
FEC0RXDV / PFEC0H2
FEC0RXD0 / PFEC0H1
FEC0CRS / PFEC0H0
FEC0TXD3 / PFEC0L7
FEC0TXD2 / PFEC0L6
FEC0TXD1 / PFEC0L5
FEC0TXER / PFEC0L4
FEC0RXD3 / PFEC0L3
FEC0RXD2 / PFEC0L2
FEC0RXD1 / PFEC0L1
FEC0RXER / PFEC0L0
FEC1TXCLK / PFEC1H7
FEC1TXEN / PFEC1H6
FEC1TXD0 / PFEC1H5
FEC1COL / PFEC1H4
FEC1RXCLK / PFEC1H3
FEC1RXDV / PFEC1H2
FEC1RXD0 / PFEC1H1
FEC1CRS / PFEC1H0
FEC1TXD3 / PFEC1L7
FEC1TXD2 / PFEC1L6
FEC1TXD1 / PFEC1L5
FEC1TXER / PFEC1L4
FEC1RXD3 / PFEC1L3
FEC1RXD2 / PFEC1L2
FEC1RXD1 / PFEC1L1
FEC1RXER / PFEC1L0
PCIBG[4:0] / PPCIBG[4:0]
PCIBR[4:0] / PPCIBR[4:0]
PSC3RTS / PPSC3PSC26
PSC3RXD / PPSC3PSC25
PSC3TXD / PPSC3PSC24
PSC2CTS / PPSC3PSC23
PSC2RTS / PPSC3PSC22
PSC2RXD / PPSC3PSC21
PSC2TXD / PPSC3PSC20
PSC1CTS / PPSC1PSC07
PSC1RTS / PPSC1PSC06
PSC1RXD / PPSC1PSC05
PSC1TXD / PPSC1PSC04
PSC0CTS / PPSC1PSC03
PSC0RTS / PPSC1PSC02
PSC0RXD / PPSC1PSC01
PSC0TXD / PPSC1PSC00
DSPISIN / PDSPI1
DSPISOUT / PDSPI1
DSPIPCS5 / PCSS / PDSPI6
DSPIPCS3 / PDSPI5
DSPIPCS2 / PDSPI4
DSPIPCS0 / SS / PDSPI3
PORT
FECI2C
FEC0EMDIO / PFECI2C3
FEC0EMDC / PFECI2C2
SCL / PFECI2C1
SDA / PFECI2C0
PORT
IRQ
1
PORT
TIM
2
IRQ[7:1] / PIRQ[5:1]
TOUT[3:0] / PTIM[7:4]
TIN[3:0] / PTIM[3:0]
1
The port IRQ GPIO functionality is provided through the EPORT module.
2
The port TIM GPIO funtionality is provided through the GPT module.