Freescale Semiconductor MCF5480 - Manual (Page 421)

External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-5
For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:
• If bursting is used, TSIZ[1:0] is driven to the size of transfer.
• If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port
size.
For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size.
For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer
on the first access and the size of the current port transfer on subsequent transfers. For example, for a
longword write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three
transactions. If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to
2’b00 for the entire transfer.
17.4.7 Byte Selects (BE/BWE[3:0])
The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data
when driven low as shown in Table 17-1 . BE/BWEn signals are asserted only to the memory bytes used
during a read or write access.
17.4.8 Output Enable (OE)
The output enable signal (OE) is sent to the interfacing memory and/or peripheral to enable a read transfer.
OE is asserted only when a chip select matches the current address decode.
17.4.9 Transfer Acknowledge (TA)
This signal indicates that the external data transfer is complete. During a read cycle, when the processor
recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the
processor recognizes TA, the bus cycle is terminated.
If auto-acknowledge is disabled, the external device drives TA to terminate the bus transfer; if
auto-acknowledge is enabled, the TA is generated internally after a specified wait states or the external
device may assert external TA before the wait-state countdown, terminating the cycle early. The MCF548x
negates FBCSn a cycle after the last TA asserts. During read cycles, the peripheral must continue to drive
data until TA is recognized. For write cycles, the processor continues to drive data one clock after FBCSn
is negated.
The number of wait states is determined either by internally programmed auto acknowledgement or by the
external TA input. If the external TA is used, the peripheral has total control on the number of wait states.
NOTE
External devices should only assert TA while the FBCSn signal to the
external device is asserted.
Table 17-2. Data Transfer Size
TSIZ[1:0] Transfer Size
00 4 bytes (longword)
01 1 byte
10 2 bytes (word)
11 16 bytes (line)