4 precharge all banks command (pall), Precharge all banks command (pall) -11 – Freescale Semiconductor MCF5480 User Manual
Page 459
SDRAM Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
18-11
issue a PALL command to close the active row. Then the SDRAMC issues ACTV to activate the necessary
row and bank for the new access, followed finally by the WRITE command.
The PALL and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going data
movement.
With both SDR and DDR memory, a read command can be issued overlapping the masked beats at the end
of a previous single write of the same SDCS; the read command aborts the remaining (unnecessary) write
beats. This is not possible with SDR memory, because SDR memory cannot be read with the masks
asserted.
18.5.1.4
Precharge All Banks Command (PALL)
The precharge command puts SDRAM into an idle state. The SDRAM must be in this idle state before a
REF, LMR, LEMR, or ACTV command to open a new row within a particular bank can be issued.
The memory controller issues the PALL command only when necessary for one of the following
conditions:
•
Access to a new row
•
Refresh interval elapsed
•
Software commanded precharge
NOTE
The SDRAMC does not support the precharge selected bank memory
command.
18.5.1.5
Load Mode/Extended Mode Register Command (LMR, LEMR)
All SDRAM devices contain mode registers that are used to configure the timing and burst mode for the
SDRAM. These commands are used to access the mode registers that physically reside within the SDRAM
devices. During the LMR or LEMR command the SDRAM will latch the address bus and load the value
into the selected mode register.
NOTE
The LMR and LEMR commands are only used during SDRAM
initialization.
The following steps should be used to write the mode register and extended mode register:
1. Set the SDCR[MODE_EN] bit.
2. Write the SDMR[BA] bits to select the mode register.
3. Write the desired mode register value to the SDMR[ADDR]. Don’t overwrite the SDMR[BA]
values.
4. Set the SDMR[CMD] bit.
5. For DDR, repeat from step 2 for the extended mode register.
6. Clear the SDCR[MODE_EN] bit.