Freescale Semiconductor MCF5480 - Manual (Page 461)

SDRAM Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 18-13
18.5.1.6 Auto Refresh Command (REF)
The memory controller issues auto refresh commands according to the SDCR[RC] value. Each time the
programmed refresh interval elapses, the memory controller issues a PALL command followed by a REF
command.
If a memory access is in progress at the time the refresh interval elapses, the memory controller schedules
the refresh after the transfer is finished; but the interval timer continues counting so that the average refresh
rate is constant.
After REF, the SDRAM is in an idle state and waits for an ACTV command.
18.5.1.7 Self-Refresh (SREF) and Power-Down (PDWN) Commands
The memory controller issues either a PDWN or a SREF command if the SDCR[CKE] bit is cleared. If
the SDCR[REF] bit is set when CKE is negated, the controller issues a SREF command; if the REF bit is
cleared, the controller issues a PDWN command. The REF bit may be changed in the same register write
that changes the CKE bit; the controller will act upon the new value of the REF bit.
Just like a REF, the controller automatically issues a PALL command before the self-refresh command.
The memory is reactivated from power-down or self-refresh mode by setting the CKE bit.
If a normal refresh interval elapses while the memory is in self-refresh mode, a PALL and REF will be
performed as soon as the memory is reactivated. If the memory is put into and brought out of self-refresh
all within a single refresh interval, the next automatic refresh will occur on schedule.
In self-refresh mode, the memory does not require an external clock. To restart periodic refresh when the
memory is reactivated, the REF bit must be reasserted. This can be done before the memory is reactivated,
or in the same control register write that sets CKE to exit self-refresh mode.
18.5.2 Power-Up Initialization
SDRAMs have a prescribed initialization sequence. The following sections detail the memory
initialization steps for both SDR and DDR SDRAM. The sequence might change slightly from
device-to-device. Refer to the device datasheet as the most relevant reference.
Table 18-5. Extended Mode Register Field Descriptions
Address
Line
Description
BA[1:0] Bank Address.
00 Does not select the extended mode register
01 Selects the extended mode register
1x Reserved
A11–A1 Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can use these
bits to implement optional features. Check with SDRAM manufacturer to determine if any optional features have
been implemented. For normal operation all bits should be cleared.
A0 Delay locked loop. Controls enabling of the delay locked loop circuitry used for DDR timing.
0 Enabled
1 Disabled.