4 sdram control register (sdcr), Sdram control register (sdcr) -20 – Freescale Semiconductor MCF5480 User Manual
Page 468
MCF548x Reference Manual, Rev. 3
18-20
Freescale Semiconductor
18.7.4
SDRAM Control Register (SDCR)
The SDCR, shown in
Figure 18-11
, controls SDRAMC operating modes including the refresh count and
address line muxing.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R MODE
_EN
CKE
DDR
REF
0
0
MUX
AP
DRIV
E
RCNT
W
Reset
Uninitialized
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
DQS_OE
0
0
0
BUFF
0
IREF
IPALL
0
W
Reset
Uninitialized
Reg
Addr
MBAR + 0x0104
Figure 18-11. SDRAM Control Register (SDCR)
Table 18-11. SDCR Field Descriptions
Bits
Name Description
31
MODE_EN Mode enable.
0 Mode register locked, cannot be written
1 Mode register enabled, can be written
30
CKE
Clock enable.
0 SDCKE is negated (low)
1 SDCKE is asserted (high)
29
DDR
DDR mode select.
0 SDR mode
1 DDR mode
28
REF
Refresh enable.
0 Automatic refresh disabled
1 Automatic refresh enabled
27–26
—
Reserved. Should be cleared.
25–24
MUX
Muxing control. Selects routing of addr[7:4] as row or column address bits as shown in
23
AP
Auto precharge control bit.
0 CA10 is the auto precharge control bit
1 Reserved