Freescale Semiconductor MCF5480 User Manual
Page 493
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-9
19.3.1.3
Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3
6
PER
Parity error response. This bit controls the device’s response to parity errors.
0 The device sets its Parity Error status bit (bit 31) in the event of a parity error, but does not assert
PERR.
1 When a parity error is detected, the PCI controller asserts PERR
5
V
VGA palette snoop enable. Fixed to 0. This bit indicates that the PCI controller is not VGA compatible.
Initialization software should write a 0 to this bit location.
4
MW
Memory write and invalidate enable. This bit is an enable for using the memory write and invalidate
command.
0 Only memory write command can be used
1 PCI controller-as-master may generate the memory write and invalidate command.
3
SP
Special cycle monitor or ignore. This bit is to determine whether or not to ignore PCI Special Cycles.
Since PCI controller-as-target does not recognize messages delivered via the Special Cycle operation,
a value of 1 should never be programmed to this register. This bit, however, is programmable
(read/write from both the IP bus and PCI bus Configuration cycles).
2
B
Bus master enable. This bit indicates whether or not the PCI controller has the ability to serve as a
master on the PCI bus. A value of 1 indicates this ability is enabled. If the PCI controller is used as a
master on the PCI bus (via the XL bus or comm bus), a 1 should be written to this bit during initialization.
If the value of the register is 0, it will not inhibit mastered transactions. This bit is meant to be read by
configuration software.
1
M
Memory access control. This bit controls the PCI controller’s response to memory space accesses.
0 The PCI controller does not recognize memory accesses
1 The PCI controller recognizes memory accesses.
0
IO
I/O access control. Fixed to 0. This bit is not implemented because there is no PCI controller I/O type
space accessible from the PCI bus. The PCI base address registers are memory address ranges only.
Initialization software should write a 0 to this bit location.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Class Code
W
Reset
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Class Code
Revision ID
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xB08
Figure 19-4. Revision ID/Class Code Register (PCICCRIR)
Table 19-4. PCISCR Field Descriptions (Continued)
Bits
Name
Description