4 configuration 1 register (pcicr1)-pci dword 3, Configuration 1 register (pcicr1)—pci dword 3 -10, 4 configuration 1 register (pcicr1)—pci dword 3 – Freescale Semiconductor MCF5480 User Manual
Page 494
MCF548x Reference Manual, Rev. 3
19-10
Freescale Semiconductor
19.3.1.4
Configuration 1 Register (PCICR1)—PCI Dword 3
Table 19-5. PCICCRIR Field Descriptions
Bits
Name
Description
31–8
Class Code This field is read-only and represents the PCI Class Code assigned to processor. Its value
is: 0x06 8000. (Other bridge device).
7–0
Revision ID This field is read-only and represents the PCI Revision ID for this version of the processor.
Its value is: 0x00.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
BIST
Header Type
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Lat Timer [7:3]
Lat Timer [2:0]
Cache Line Size [7:4]
Cache Line Size [3:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xB0C
Figure 19-5. Configuration 1 Register (PCICR1)
Table 19-6. PCICR1 Field Descriptions
Bits
Name
Description
31–24
BIST
Built in self test. Fixed to 0x00. The PCI controller does not implement the Built-In Self Test
register. Initialization software should write a 0x00 to this register location.
23–16
Header
Type
Header type. Fixed to 0x00. The PCI controller implements a Type 0 PCI configuration
space Header. Initialization software should write a 0x00 to this register location.
15–11
Lat Timer
Latency timer [7:3]. This register contains the latency timer value, in PCI clocks, used when
the PCI controller is the PCI master. The upper five bits are programmable.
Latency timer must be programmed to a non-zero value before the PCI Controller will
operate as master of the PCI bus.
10-8
Latency timer [2:0] The lower three bits of the register are hardwired low
7–4
Cache Line
Size
Cache line size[7:4] Specifies the cache line size in units of DWORDs. The higher four bits
of the register are hardwired low
3–0
Cache line size [3:0] Specifies the cache line size in units of DWORDs.