6 base address register 1 (pcibar1)-pci dword 5, 7 cardbus cis pointer register pciccpr-pci dword a, Base address register 1 (pcibar1)—pci dword 5 -12 – Freescale Semiconductor MCF5480 User Manual
Page 496
MCF548x Reference Manual, Rev. 3
19-12
Freescale Semiconductor
19.3.1.6
Base Address Register 1 (PCIBAR1)—PCI Dword 5
19.3.1.7
CardBus CIS Pointer Register PCICCPR—PCI Dword A
This optional register contains the pointer to the Card Information Structure (CIS) for the CardBus card.
All 32 bits of the register are programmable by the slave bus. From the PCI bus, this register can only be
read, not written. Its reset value is 0x0000 0000 and is accessible at address MBAR + 0xB28.
19.3.1.8
Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B
The Subsystem Vendor ID register contains the 16-bit manufacturer identification number of the add-in
board or subsystem that contains this PCI device. The Subsystem ID register contains the 16-bit subsystem
identification number of the add-in board or subsystem that contains this PCI device. A value of zero in
these registers indicates there isn’t a Subsystem Vendor and Subsystem ID associated with the device. If
used, software must write to these registers before any PCI bus master reads them.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
BAR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
PREF
RANGE
IO/M#
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Reg
Addr
MBAR + 0xB14
Figure 19-7. Base Address Register 1 (PCIBAR1)
Table 19-8. PCIBAR1 Field Descriptions
Bits
Name
Description
31–30
BAR1
Base address register 1. Processo PCI base address register 1 (1 Gbyte). Applies only
when the processor is target. These bits are programmable (read/write from both the IP
bus and PCI bus Configuration cycles).
29–4
—
Reserved, should be cleared.
3
PREF
Prefetchable access. Fixed to 1. This bit indicates that the memory space defined by BAR1
is prefetchable. Configuration software should write a 1 to this bit location.
2–1
RANGE
Fixed to 00. This register indicates that base address 1 is 32 bits wide and can be mapped
anywhere in 32-bit address space. Configuration software should write 00 to these bit
locations.
0
IO/M#
IO or memory space. Fixed to 0. This bit indicates that BAR1 is for memory space.
Configuration software should write a 0 to this bit location.
0 Memory
1 I/O