2 tx start address register (pcitsar) – Freescale Semiconductor MCF5480 User Manual
Page 508
MCF548x Reference Manual, Rev. 3
19-24
Freescale Semiconductor
19.3.3.1.2
Tx Start Address Register (PCITSAR)
Table 19-19. PCITPSR Field Descriptions
Bits
Name
Description
31–18
Packet_Size
Packet_Size [15:2]. The Packet_Size field indicates the number of bytes for the transmit controller
to send over PCI. Only bits [15:2] are writable. Only 32-bit data transfers to the FIFO are allowed.
Writing to this register also completes a Restart Sequence as long as the Master Enable bit,
PCITER[ME], is high and Reset Controller bit, PCITER[RC], is low.
17–16
Packet_Size [1:0] The two low bits are hardwired low.
15–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8404
Figure 19-21. Tx Start Address Register (PCITSAR)
Table 19-20. PCITSAR Field Descriptions
Bits
Name
Description
31–0
Start_Add
User writes the PCI address to be presented for the first DWORD of a PCI packet. The PCI Tx
controller will track and calculate the necessary address for subsequent transactions. Addressing
is assumed to be sequential from the start address unless the PCITTCR[DI] bit is set. This register
will not increment as the PCI packet proceeds.