6 rx done counts register (pcirdcr) – Freescale Semiconductor MCF5480 User Manual
Page 525
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-41
19.3.3.2.6
Rx Done Counts Register (PCIRDCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Bytes_Done
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Packets_Done
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8498
Figure 19-39. Rx Done Counts Register (PCIRDCR)
Table 19-38. PCIRDCR Field Descriptions
Bits
Name
Description
31–16
Bytes_Done
This status register indicates the number of bytes received since the start of a packet. It is
updated at the end of each successful PCI data beat. For normally terminated packets, the
Bytes_Done value and the Packet_Size values are equal. If Continuous Mode is active, the
Bytes_Done value operates the same way. When the restart occurs for a continuous packet,
however, Bytes_Done will read 0 and the Packets_Done field will increment.
15–0
Packets_Done This status register indicates the number of previous packets received. It is active only if
continuous mode is in effect. If the either of the following occurs, the counter is reset:
• Reset Controller bit, PCIRER[RC], is asserted (normal way to restart continuous mode)
• Master Enable bit, PCIRER[ME], is negated during the current PCI data transmission and left
negated until the NT status bit asserts
The Master Enable bit, if negated as described, resets the Packets_Done status without
disturbing continuous mode addressing..
At any point in time the total number of bytes received can be calculated as:
(Packets_Done
× Packet_Size) + Bytes_Done
This assumes Packet_Size is the same for all restart sequences and the Packets_Done register
has not been cleared.