7 rx status register (pcirsr) – Freescale Semiconductor MCF5480 User Manual
Page 526
MCF548x Reference Manual, Rev. 3
19-42
Freescale Semiconductor
19.3.3.2.7
Rx Status Register (PCIRSR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
NT
BE3
BE2
BE1
FE
SE
RE
TA
IA
W
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x849C
1
Bits 24-16 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
Figure 19-40. Rx Status Register (PCIRSR)
Table 19-39. PCIRSR Field Descriptions
Bits
Name
Description
31–25
—
Reserved, should be cleared.
24
NT
Normal Termination. This bit is set when any packet terminates normally. It is not set for abnormally
terminated packets. An interrupt will be generated by this condition if the PCIRER[NE] bit is set.
This bit is cleared by writing ‘1’ to it.
23
BE3
Bus Error type 3. This bit is set whenever a Slave bus transaction attempts to write to a Read-Only
register. This flag bit is set regardless of the Bus error Enable bit (BE). If software is polling and
wishes to disregard this error it must mask this bit out. No corruption of the register bits occur for
this (or any other) Bus Error case. This bit is cleared by writing ‘1’ to it.
22
BE2
Bus Error type 2.This bit is set whenever a Slave bus transaction attempts to write to a Reserved
register (an entire 32-bit register, not just a Reserved bit or byte). This bit is set regardless of the
Bus error Enable bit (BE). If software is polling and wishes to disregard this error it must mask this
bit out.This bit is cleared by writing ‘1’ to it.
21
BE1
Bus Error type 1. This bit is set whenever a Slave bus transaction attempts to read a Reserved
register (an entire 32-bit register, not just a Reserved bit or byte). This bit is set regardless of the
Bus error Enable bit (BE). If software is polling and wishes to disregard this error it must mask this
bit out.This bit is cleared by writing ‘1’ to it.
20
FE
FIFO Error. This bit is set whenever the Receive FIFO asserts an unmasked error bit. An interrupt
will be generated by this condition if the PCIRER[FEE] bit is set.The source of the error must be
determined by reading the FIFO status register PCIRFSR. Also, the error condition must be cleared
at the FIFO prior to clearing this Sticky bit or this flag will continue to assert. This bit is cleared by
writing ‘1’ to it.
19
SE
System error. This bit is set in response to the Receive Controller entering an illegal state. System
error indicates a malfunction of the block and should not occur in normal operation. An interrupt can
be generated by this condition if the PCIRER[SE] bit is set. In normal operation this should never
occur. The only recovery is to assert the reset controller bit, PCIRER[RC], and clear this flag by
writing ‘1’ to it.