Freescale Semiconductor MCF5480 - Manual (Page 533)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 19-49
19.4.1.2 Basic Transfer Control
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one
or more data phases. Fundamentally, all PCI data transfers are controlled by three signals PCIFRAME,
PCIIRDY, and PCITRDY. An initiator asserts PCIFRAME to indicate the beginning of a PCI bus
transaction and negates PCIFRAME to indicate the end of a PCI bus transaction. An initiator negates
PCIIRDY to force wait cycles. A target negates PCITRDY to force wait cycles.
The PCI bus is considered idle when both PCIFRAME and PCIIRDY are negated. The first clock cycle in
which PCIFRAME is asserted indicates the beginning of the address phase. The address and bus command
code are transferred in that first cycle. The next cycle begins the first of one or more data phases. Data is
transferred between initiator and target in each cycle that both PCIIRDY and PCITRDY are asserted. Wait
cycles may be inserted in a data phase by the initiator (by negating PCIIRDY) or by the target (by negating
PCITRDY).
Once an initiator has asserted PCIIRDY, it cannot change PCIIRDY or PCIFRAME until the current data
phase completes regardless of the state of PCITRDY. Once a target has asserted PCITRDY or PCISTOP,
it cannot change DEVSEL, PCITRDY, or PCISTOP until the current data phase completes. In simpler
terms, once an initiator or target has committed to the data transfer, it cannot back out.
When the initiator intends to complete only one more data transfer (which could be immediately after the
address phase), PCIFRAME is negated and PCIIRDY is asserted (or kept asserted) indicating the initiator
is ready. After the target indicates the final data transfer (by asserting PCITRDY), the PCI bus may return
to the idle state (both PCIFRAME and PCIIRDY are negated) unless a fast back-to-back transaction is in
progress. In the case of a fast back-to-back transaction, an address phase immediately follows the last
phase.
19.4.1.3 PCI Transactions
The figures in this section show the basic “memory read” and “memory write” command transactions.
Figure 19-47 shows a PCI burst read transaction (2-beat). The signal PCIFRAME is driven low to initiate
the transfer. Cycle 1 is the address phase with valid address information driven on the AD bus and a PCI
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Dual Address Cycle
1110 Memory Read Line
1111 Memory Write and Invalidate
Table 19-46. PCI Command Encodings (Continued)
PCICXBE[3:0] Command Type