Freescale Semiconductor MCF5480 - Manual (Page 537)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 19-53
As an initiator, the MCF548x supports both linear incrementing and cache wrap mode. For memory
transactions, when an XL bus burst transaction is wrapped, the cache wrap mode is automatically
generated. For zero-word-aligned bursts and single-beat transactions, the MCF548x drives AD[1:0] to
0b00.
As a target, the MCF548x treats cache wrap mode as a reserved memory mode when the cache line size
register is programmed zero. The MCF548x will return the first beat of data and then signal a disconnect
without data on the second data phase.
19.4.1.5.2 I/O Space Addressing
For PCI I/O accesses, all 32 address signals are used to provide an address with granularity of a single byte.
Once a target has claimed an I/O access, it must determine if it can complete the entire access as indicated
by the byte enable signals. If all the selected bytes are not in the address range of the target, the entire
access cannot complete. In this case, the target does not transfer any data, and terminates the transaction
with a target-abort.
19.4.1.5.3 Configuration Space Addressing and Transactions
PCI supports two types of configuration accesses. Their primary difference is the format of the address on
the PCIAD[31:0] signals during the address phase.
The two low-order bits of the address indicate the format used for the configuration address phase: type 0
(AD[1:0] = 0b00) or type 1 (AD[1:0] = 0b01). Both address formats identify a specific device and a
specific configuration register for that device:
• Type 0 configuration accesses are used to select a device on the local PCI bus. They do not
propagate beyond the local PCI bus and are either claimed by a local device or terminated with a
master-abort.
• Type 1 configuration accesses are used to target a device on a subordinate bus through a PCI-to-PCI
bridge, see Figure 19-51 . Type 1 accesses are ignored by all targets except PCI-to-PCI bridges that
pass the configuration request to another PCI bus.
When the controller initiates a configuration access on the PCI bus, it places the configuration address
information on the AD bus and the configuration command on the PCICXBE[3:0] bus. A Type 0
configuration transaction is indicated by setting AD[1:0] to 0b00 during the address phase. The bit pattern
Table 19-48. PCI I/O Space Byte Decoding
Access Size PCIAD[1:0] PCICXBE[3:0] Data
8-bit 00 xxx0 AD[7:0]
01 xx01 AD[15:8]
10 x011 AD[23:16]
11 0111 AD[31:24]
16-bit 00 xxx0 AD[15:0]
01 xx01 AD[23:8]
10 x011 AD[31:16]
24-bit 00 xxx0 AD[23:0]
01 xx01 AD[31:8]
32-bit 00 xxx0 AD[31:0]