Freescale Semiconductor MCF5480 - Manual (Page 548)

MCF548x Reference Manual, Rev. 3
19-64 Freescale Semiconductor
Upon detection of a PCI address phase, the PCI controller decodes the address and bus command to
determine if the transaction is for local memory (BAR0 or BAR1 hit). If the transaction falls within
MCF548x PCI space (memory only), the PCI Controller target interface asserts DEVSEL, latches the
address, decodes the PCI bus command, and forwards them to the internal control unit. On writes, data is
forwarded along with the byte enables to the internal gasket. On reads, four bytes of data are provided to
the PCI bus and the byte enables determine which byte lanes contain meaningful data. If no byte enables
are asserted, MCF548x completes a read access with valid data and completes a write access by discarding
the data internally. All target transactions will be translated into XL bus master transactions.
There are two address translation registers that must be initialized before data transfer can begin. These
address registers correspond to BAR0 and BAR1 in MCF548x PCI Type 00h Configuration space register
(PCI space). When there is a hit on MCF548x PCI base address ranges (0 or 1), the upper bits of the address
are written over by this register value to address some space in MCF548x. One 256-Kbyte base address
range (BAR0) maps to non-prefetchable local memory and one 1-Gbyte range (BAR1) targeted to
prefetchable memory.
19.4.5.1 Reads from Local Memory
MCF548x can provide continuous data to a PCI master using two 32-byte buffers. The PCI controller
bursts reads internally at each 32-byte PCI address boundary. The data is stored in the first 32-byte buffer
until either the PCI master flushes the data or the transaction terminates (PCIFRAME deasserts). For
prefetchable memory (BAR1 space), the next line can be fetched from memory in anticipation of the next
PCI request and stored in the second buffer. Prefetching is performed for BAR1 addressed transactions if
the PCI command is a Memory Read Multiple or the prefetch bit is set in the Target Control Register
(PCITCR).
19.4.5.2 Local Memory Writes
The target interface always posts writes. This allows for data to be latched while waiting for internal access
to local memory.While PCI burst transactions are accepted, writes are sent out on the internal bus as
single-beat. A 32-byte posted write buffer is implemented to improve data throughput.
If the PCI controller aborts the transaction in the middle of PCI burst due to internal conflicts, the external
master recognizes some of the data as transferred. (Subsequent transfers of a burst will be aborted on PCI
bus). The external PCI master must query the “Target abort signalled” bit in the PCI Type 00h
configuration status register to determine if a target abort occurred.
19.4.5.3 Data Translation
The XL bus supports misaligned operations, however, it is strongly recommended that software attempt to
transfer contiguous code and data where possible. Non-contiguous transfers degrade performance.
PCI-to-XL bus transaction data translation is shown in Table 19-53 and Table 19-54 .