Freescale Semiconductor MCF5480 - Manual (Page 563)

Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 20-3
20.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI
arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the
MCF548x needs to initiate a PCI transaction.
20.2.6 External Bus Request (PCIBR[4:1])
The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.
20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN)
The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus.
When the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus,
PCIGNTIN. It is driven by an external PCI arbiter.For detailed description of the PCI bus signals, see the
PCI Local Bus Specification, Revision 2.2.
20.3 Register Definition
The PCI arbiter provides decode logic for up to sixty-four 32-bit registers, but makes use of just two.
Accesses via the slave interface to and from the registers can be 8-bit, 16-bit, or 32-bit accesses. Reads to
unimplemented registers return 0x0000_0000 and writes have no effect.
All registers are accessible at an offset of MBAR in the memory space. There is one module offset for PCI
arbiter space at 0x0C00. Refer to for module offsets.
20.3.1 PCI Arbiter Control Register (PACR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DS 0 0 0 0 0 0 0 0 0 EXTMINTEN INTMINTEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 EXTMPRI INTMPRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xC00
Figure 20-2. PCI Arbiter Control Register (PACR)