Freescale Semiconductor MCF5480 - Manual (Page 565)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 20-5
20.3.2 PCI Arbiter Status Register (PASR)
20.4 Functional Description
20.4.1 External PCI Requests
An external PCI master may target the MCF548x or external slaves. The request/grant handshake always
precedes any PCI bus operation. The PCI arbiter must service access requests for an external
master-to-external target transactions as well as external master-to-MCF548x transactions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 EXTMBK ITLMBK
W rwc
1
rwc
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xC04
1 Bits 21-16 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit
that is currently a 0 or writing a 0 to any rwc bit has no effect.
Figure 20-3. PCI Arbiter Status Register (PASR)
Table 20-3. PASR Field Descriptions
Bits Name Description
31–22 — Reserved. Software should write zero to this register.
21–17 EXTMBK External master broken: External master time-out. Bit 17 reports the time-out status for the device
using REQ0 and GNT0 pins, bit 18 for REQ1 and GNT1, etc. A CPU interrupt will be generated if
the corresponding external master interrupt enable bit is set. Software must write a 1 to each bit
location to clear.
16 ITLMBK Internal master broken: An MCF548xmaster time-out occurred. A CPU interrupt will be generated
if the internal master interrupt enable bit is set. Software must write a 1 to this bit location to clear.
15–0 — Reserved. Software should write zero to this register.