Freescale Semiconductor MCF5480 - Manual (Page 566)

MCF548x Reference Manual, Rev. 3
20-6 Freescale Semiconductor
20.4.2 Arbitration
20.4.2.1 Hidden Bus Arbitration
PCI bus arbitration can take place while the currently granted device is performing a bus transaction if
another master is requesting access to the bus. As long as the bus is active, the arbiter can deassert GNT
to one master and assert GNT to the next in the same cycle and no PCI bus cycles are consumed due to
arbitration. The newly granted device must wait until the bus is relinquished by the current master before
initiating a transaction.
20.4.2.2 Arbitration Scheme
The MCF548x PCI bus master logic provides a programmable two-level least recently used (LRU) priority
algorithm. Two groups of masters are assigned, a high-priority group and a low-priority group. The
low-priority group as a whole represents one entry in the high-priority group. If the high-priority group
consists of n masters, then in at least every n+1 transactions, the highest priority is assigned to the
low-priority group. Low-priority masters have equal access to the bus with respect to other low-priority
masters. If there are masters programmed into both groups, masters in the high-priority group can be
serviced n transactions out of n+1, while one master in the low-priority group is serviced once every n+1
transactions. If all masters are programmed to the same group, or if there is only one master assigned to
the low-priority group, then there is no priority distinction among masters.
A LRU priority scheme allows for “fairness” in priority resolution because no one master can prevent other
masters from gaining access to the bus. The priority level, high or low, provides a simple weighting
mechanism for master access to the bus.
Priority in a LRU scheme adjusts so that the last master serviced is assigned the lowest priority in its level.
Masters with lower priority shift to the next higher priority position. The MCF548x is positioned before
all external devices in priority. If a master is not requesting the bus, its transaction slot is given to the next
requesting device within its priority group.
During hidden arbitration, GNT given to a requesting master while the PCI bus is active may be removed
and awarded to a higher priority device if a higher priority device asserts its request. If the bus is idle when
a device requests the bus, the arbiter deasserts the currently asserted GNT for one PCI clock cycle. The
arbiter evaluates the priorities of all requesting devices and grants the bus to the highest priority device in
the next cycle.
Figure 20-4 shows the initial state of the arbitration algorithm. Two devices are assigned high-priority (the
MCF548x and one external master) and four low-priority. If all masters request the use of the PCI bus
continuously, the GNT sequence is the MCF548x, device 1, device 0, the MCF548x, device 1, device 2,
the MCF548x, device 1, device 3, the MCF548x, device 1, device 4 repeating.
If device 1 is not requesting the bus, the GNT sequence is the MCF548x, device 0, the MCF548x, device
2, the MCF548x, device 3, the MCF548x, device 4 repeating. If, after this sequence completes, all devices
request the bus (including now device 1), the arbiter will assign GNT to device 1 since it has been the
longest since device 1 has used the bus. (It has highest priority.) Once all requests are serviced, the priority
resets to the initial state.