Freescale Semiconductor MCF5480 - Manual (Page 574)

MCF548x Reference Manual, Rev. 3
21-4 Freescale Semiconductor
• The prescaler is disabled, thus halting all CAN bus communication.
• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.
• The FlexCAN loses synchronization with the CAN bus, and the NOTRDY and FRZACK bits in
CANMCR are set.
• The CPU is allowed to read and write the error counter registers (in other modes they are
read-only).
After engaging one of the mechanisms to place the FlexCAN in freeze mode, the user must wait for the
FRZACK bit to be set before accessing any other registers in the FlexCAN, otherwise unpredictable
operation may occur. In freeze mode, all memory mapped registers are accessible.
To exit freeze mode, the BKPT line must be negated or the HALT bit in CANMCR must be cleared. Once
freeze mode is exited, the FlexCAN will resynchronize with the CAN bus by waiting for 11 consecutive
recessive bits before beginning to participate in CAN bus communication.
21.1.4.3 Module Disabled Mode
This mode disables the FlexCAN module; it is entered by setting CANMCR[MDIS]. If the module is
disabled during freeze mode, it shuts down the system clocks, sets the LPMACK bit, and clears the
FRZACK bit.
If the module is disabled during transmission or reception, FlexCAN does the following:
• Waits to be in either idle or bus-off state, or else waits for the third bit of intermission and then
checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in, and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the system clocks
The bus interface unit continues to operate, enabling the CPU to access memory mapped registers, except
the free-running timer, the error counter register and the message buffers, which cannot be accessed when
the module is disabled. Exiting from this mode is done by negating the MDIS bit, which will resume the
clocks and negate the LPMACK bit.
21.1.4.4 Loop-Back Mode
The module enters this mode when the LPB bit in the control register is set. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN
output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting and
treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception
of its own message. Both transmit and receive interrupts are generated.
21.1.4.5 Listen-Only Mode
In listen-only mode, the FlexCAN module is able to receive messages without giving an acknowledgment.
Whenever the module enters this mode, the status of the error counters is frozen and the FlexCAN module
operates like in error passive mode. Because the module does not influence the CAN bus in this mode, the
host device is capable of functioning like a monitor or for automatic bit-rate detection.