Freescale Semiconductor MCF5480 - Manual (Page 582)

MCF548x Reference Manual, Rev. 3
21-12 Freescale Semiconductor
21.3.2.4.1 FlexCAN Rx Global Mask Register (RXGMASK)
The Rx global mask bits are applied to all Rx identifiers, excluding Rx buffers 14
–
15 that have their
specific Rx mask registers. Access to this register is unrestricted.
Rx_Msg in 2 1 1 1 1 1 1 1 1 0 0 1 0 2 2
Rx_Msg in 3 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 3
Rx_Msg in 4 0 1 1 1 1 1 1 1 0 0 0 0 4
Rx_Msg in 5 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14 5
RX14MASK 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Rx_Msg in
6
1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
6
Rx_Msg in
7
0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14
7
1 Match for Extended Format (MB3).
2
Match for Normal Format. (MB2).
3
Mismatch for MB3 because of ID0.
4 Mismatch for MB2 because of ID28.
5 Mismatch for MB3 because of ID28, Match for MB14 (Uses RX14MASK).
6
Mismatch for MB14 because of ID27 (Uses RX14MASK).
7
Match for MB14 (Uses RX14MASK).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0xA010 (RXGMASK0); 0xA810 (RXGMASK1)
Figure 21-7. FlexCAN Rx Global Mask Register (RXGMASK)
Table 21-5. RXGMASK Field Descriptions
Bits Name Description
31–29 — Reserved, should be cleared.
Table 21-4. Mask Examples for Normal/Extended Messages (Continued)
Base ID
ID28.................ID18
IDE
Extended ID
ID17......................................ID0
Match