Freescale Semiconductor MCF5480 - Manual (Page 59)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 1-1
Chapter 1
Overview
This chapter provides an overview of the MCF548x microprocessor features, including the major
functional components.
1.1 MCF548x Family Overview
The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4
central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit
(MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers
for caches and local data memories. The MCF548x family is capable of performing at an operating
frequency of up to 200 MHz or 308 MIPS (Dhrystone 2.1).
To maximize throughput, the MCF548x family incorporates three independent external bus interfaces:
1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals
and has up to six chip selects.
2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate
(DDR) bus that can run at up to one-half of the CPU core frequency. The glueless DDR SDRAM
controller handles all address multiplexing, input and output strobe timing, and memory bus clock
generation.
3. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency
of 33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for
bus mastership, and access to internal MCF548x memory resources.
The MCF548x family provides substantial communications functionality by integrating the following
connectivity peripherals:
• Up to two 10/100 Mbps fast Ethernet controllers (FECs)
• One optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver
• Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs)
• One DMA serial peripheral interface (DSPI)
• One inter-integrated circuit (I
2
C
™
) bus controller
• Two controller area network 2.0B (FlexCAN) interfaces with 16 message buffers each
Additionally, the MCF548x provides hardware support for a range of Internet security standards with an
optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and
AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and
random number generation. Hardware acceleration of these functions is critical to avoiding the throughput
bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and
other security standards. The incorporation of cryptography acceleration makes the MCF548x family a
compelling solution for a wide range of office automation, industrial control, and SOHO networking
devices that must have the ability to securely transmit critical equipment control information across
typically insecure Ethernet data networks.
Additional features of MCF548x products include a watchdog timer, two 32-bit slice timers for RTOS
scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and
pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL)
to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple
general-purpose I/O ports.