Freescale Semiconductor MCF5480 - Manual (Page 593)

Functional Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-23
Figure 21-13. FlexCAN Message Buffer Memory Map
21.4.3 Transmit Process
The CPU prepares or changes an MB for transmission by executing the following steps:
1. Writing the control/status word to hold Tx MB inactive (CODE = 0b1000).
2. Writing the ID word.
3. Writing the data bytes.
4. Writing the control/status word (active CODE, LENGTH).
NOTE
The first and last steps are mandatory!
Once the MB is activated in the fourth step, it will participate in the arbitration process which takes place
every time the CAN bus is sensed as free by the receiver or at the inter-frame space, and there is at least
one MB ready for transmission. This internal arbitration process is intended to select the MB from which
the next frame is transmitted.
Control/Status
8 byte Data fields
0x80
0x84
0x88
Message Buffer 0
Message Buffer 1
Message Buffer 2
Message Buffer 15
0x8F
0x90
0xA0
0x170
Message Buffers
0x17F
0x9F
0xAF
0xB0
0x16F
FlexCAN Base
Address Offset
Message Buffer 3
through
Message Buffer 14
Identifier