Freescale Semiconductor MCF5480 - Manual (Page 595)

Functional Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-25
was captured at the beginning of the ID field on the CAN bus) is written into the TIMESTAMP field in the
MB, the ID field, data field (8 bytes at most) and the LENGTH field are stored, the CODE field is updated
and a status flag is set in the IFLAG register.
The CPU should read a receive frame from its MB in the following way:
1. Read the control/status word (mandatory—activates internal lock for this buffer).
2. Read the ID (optional—needed only if a mask was used).
3. Read the Data field words.
4. Read the free-running timer (releases internal lock —optional).
Upon reading the control and status word, if the BUSY bit is set in the CODE field, then the CPU should
defer the access to the MB until this bit is negated. Reading the free running timer is not mandatory. If not
executed, the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a
single MB is locked at a time. The only mandatory CPU read operation is the one on the control and status
word to assure data coherency.
The CPU should synchronize to frame reception by the status flag for the specific MB (see
Section 21.3.2.8, “Interrupt Flag Register (IFLAG) ”), and not by the control/status word CODE field for
that MB. This is because polling the control/status word may lock the MB (see above), and the CODE field
may change before the full frame is received into the MB. The CPU should synchronize to frame reception
by the status flag bit for the specific MB in one of the IFLAG registers and not by the CODE field of that
MB. Polling the CODE field does not work because once a frame was received and the CPU services the
MB (by reading the C/S word followed by unlocking the MB), the CODE field will not return to EMPTY.
It will remain FULL, as explained in Table 21-14 . If the CPU tries to workaround this behavior by writing
to the C/S word to force an EMPTY code after reading the MB, the MB is actually deactivated from any
currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may
be lost. In summary, never do polling by directly reading the C/S word of the MBs. Instead, read the
IFLAG registers.
Note that the received identifier field is always stored in the matching MB, thus the contents of the
identifier field in a MB may change if the match was due to mask.
21.4.5.1 Self-Received Frames
Self-received frames are frames that are sent by the FlexCAN and received by itself. The FlexCAN sends
a frame externally through the physical layer onto the CAN bus, and if the ID of the frame matches the ID
of the FlexCAN MB, then the frame will be received by the FlexCAN. Such a frame is a self-received
frame. Note that FlexCAN does not receive frames transmitted by itself if another device on the CAN bus
has an ID that matches the FlexCAN Rx MB ID.
21.4.6 Message Buffer Handling
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described
in Section 21.4.3, “Transmit Process ” and Section 21.4.5, “Receive Process .” Any form of CPU accessing
a MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an
unpredictable way.
Deactivation of a message buffer (MB) is a host action that causes that message buffer to be excluded from
FlexCAN transmit or receive processes. Any CPU write access to a control/status word of MB structure
deactivates that MB, thus excluding it from Rx/Tx processes.
The match/arbitration processes are performed only during one period by the FlexCAN. Once a winner or
match is determined, there is no re-evaluation whatsoever, in order to ensure that a receive frame is not