Freescale Semiconductor MCF5480 - Manual (Page 600)

MCF548x Reference Manual, Rev. 3
21-30 Freescale Semiconductor
If PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the scheduled
sync segment.
• If the prescaler and bit timing control fields are programmed to values that result in fewer than ten
system clock periods per CAN bit time and the CAN bus loading is 100%, anytime the rising edge
of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of the
intermission between messages, the FlexCAN may not be able to prepare a message buffer for
transmission in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
• The FlexCAN bit time must be programmed to be greater than or equal to eight system clocks, or
correct operation is not guaranteed. Refer to Application Note AN1798, CAN Bit Timing
Requirements, for more details.
21.4.10 FlexCAN Error Counters
There are two error counters in the FlexCAN: transmit error counter (TXECTR), and receive error counter
(RXECTR). The rules for increasing and decreasing these counters are described in the CAN protocol, and
are fully implemented in the FlexCAN.
Each counter comprises the following:
• 8 bit up/down counter
• Increment by 8 (RXECTR also by 1)
• Decrement by 1
• Avoid decrement when equal to zero
• RXECTR preset to a value 119 ≤ x ≤ 127
• Value after reset = zero
• Detect values for error passive, bus off, and error active transitions and for alerting the host
Both counters are read only (except for freeze and halt modes).
The FlexCAN responds to any bus state as described in the protocol, e.g. transmit error active or error
passive flag, delay its transmission start time (error passive), and avoid any influence on the bus when in
the bus off state. The following are the basic rules for FlexCAN bus state transitions:
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the error status register is updated to reflect it (set error passive state).
• If the FlexCAN state is error passive, and either TXECTR counter or RXECTR then decrements
to a value less than or equal to 127 while the other already satisfies this condition, the
ERRSTAT[FLTCONF] field is updated to reflect it (set error active state).
• If the value of the TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is
updated to reflect it (set bus off state) and an interrupt may be issued. The value of TXECTR is
then reset to zero.
• If the FlexCAN state is bus off, then TXECTR, together with an internal counter are cascaded to
count the 128 occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset to
zero, and counts in a manner where the internal counter counts 11 such bits and then wraps around
while incrementing the TXECTR. When TXECTR reaches the value of 128,
ERRSTAT[FLTCONF] is updated to be error active, and both error counters are reset to zero. At
any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the
internal counter resets itself to zero, but does not affect the TXECTR value.
• If during system start-up, only one node is operating, then its TXECTR increases with each
message it is trying to transmit as a result of ACKERR. A transition to bus state error passive
should be executed as described, while this device never enters the bus off state.