Freescale Semiconductor MCF5480 - Manual (Page 64)

MCF548x Reference Manual, Rev. 3
1-6 Freescale Semiconductor
The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to
the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE)
Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit,
double-precision floating point data and supports single-precision and signed integer input operands. The
FPU programming model is like that in the MC68060 microprocessor. The FPU is intended to accelerate
the performance of certain classes of embedded applications, especially those requiring high-speed
floating point arithmetic computations.
The ColdFire V4e processor also incorporates the ColdFire memory management unit (MMU), which
provides virtual-to-physical address translation and memory access control. The MMU consists of
memory-mapped control, status, and fault registers that provide access to translation lookaside buffers
(TLBs). Software can control address translation and access attributes of a virtual address by configuring
MMU control registers and loading TLBs. With software support, the MMU provides demand-paged,
virtual addressing.
The ColdFire V4e core implements the ColdFire instruction set architecture revision B with support for
floating Point instructions. Additionally, the ColdFire V4e core includes the enhanced
multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a
4-stage execution pipeline, optimized for 32 x 32-bit operations, with support for four 48-bit accumulators.
Supported operands include 16- and 32-bit signed and unsigned integers, as well as signed fractional
operands and a complete set of instructions to process these data types. The EMAC provides superb
support for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
Refer to
Chapter 3, “ColdFire Core ,” for detailed information on the ColdFire V4e core architecture.
1.4.2 Debug Module (BDM)
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators.
The MCF548x debug module provides support in three different areas:
• Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.
• Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel.
• Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot permit. Debug interrupts let real-time systems execute a unique
service routine that can quickly save key register and variable contents and return the system to
normal operation without halting. External development systems can access saved data, because
the hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur.
1.4.3 JTAG
The MCF548x family supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting
of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit