1 aesu register map, 2 aesu reset control register (aesrcr), Aesu register map -50 – Freescale Semiconductor MCF5480 User Manual

Page 652: Aesu reset control register (aesrcr) -50, P. 22-50, Table 22-33, Describes rng interrupt

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MCF548x Reference Manual, Rev. 3

22-50

Freescale Semiconductor

22.12 Advanced Encryption Standard Execution Units (AESU)

This section contains details about the Advanced Encryption Standard Execution Units (AESU), including

detailed register map, modes of operation, status and control registers.

22.12.1 AESU Register Map

The registers used in the AESU are documented primarily for debug and target mode operations. If the

SEC requires the use of the AESU when acting as an initiator, accessing these registers directly is

unnecessary. The device drivers and the on-chip controller will abstract register level access from the user.
The AESU contains the following registers:

Reset control register

Status register

Interrupt status register

Interrupt control register

22.12.2 AESU Reset Control Register (AESRCR)

This register allows three levels reset of just AESU, as defined by the three self-clearing bits.

Table 22-33. RNGIMR Field Descriptions

Bits

Name

Description

31

ME

Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled

30

AE

Address Error. An illegal read or write address was detected within the MDEU address
space.
0 Address error enabled
1 Address error disabled

29–26

Reserved

25

OFU

Output FIFO Underflow. RNG Output FIFO has been read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled

24–21

Reserved

20

IE

Internal Error. An internal processing error was detected while generating random
numbers.
0 Internal error enabled
1 Internal error disabled

19–0

Reserved

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