Freescale Semiconductor MCF5480 - Manual (Page 67)

MCF548x Family Features
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 1-9
• 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM
1.4.6.4 Programmable Serial Controllers (PSCs)
The MCF548x product family supports four PSCs that can be independently configured to operate in the
following modes:
• Universal asynchronous receiver transmitter (UART) mode
— 5,6,7,8 bits of data plus parity
— Odd, even, none, or force parity
— Stop bit width programmable in 1/16 bit increments
— Parity, framing, and overrun error detection
— Automatic PSCCTS and PSCRTS modem control signals
• IrDA 1.0 SIR mode (SIR)
— Baud rate range of 2400–115200 bps
— Selectable pulse width: either 3/16 of the bit duration or 1.6
µs
• IrDA 1.1 MIR mode (MIR)
— Baud rate of 0.576 or 1.152 Mbps
• IrDA 1.1 FIR mode (FIR)
— Baud rate of 4.0 Mbps
• 8-bit soft modem mode (modem8)
• 16-bit soft modem mode (modem16)
• AC97 soft modem mode (AC97)
Each PSC supports synchronous (USART) and asynchronous (UART) protocols. The PSCs can be used to
interface to external full-function modems or external codecs for soft modem support, as well as IrDA 1.1
or 1.0 interfaces. Both 8- and 16-bit data widths are supported. PSCs can be configured to support a
1200-baud plain old telephone system (POTS) modem, V.34 or V.90 protocols. The standard UART
interface supports connection to an external terminal/computer for debug support.
1.4.6.5 I
2
C (Inter-Integrated Circuit)
The MCF548x product family provides an I
2
C two-wire, bidirectional serial bus for on-board
communication. It features the following:
• Multimaster operation with arbitration and collision detection
• Calling address recognition and interrupt generation
• Automatic switching from master to slave on arbitration loss
• Software-selectable acknowledge bit
• Start and stop signal generation and detection
• Bus busy status detection
1.4.6.6 DMA Serial Peripheral Interface (DSPI)
The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.
Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed
by host software or by the system DMA controller. The DSPI supports these SPI features:
• Full-duplex, three-wire synchronous transfers
• Master and slave mode—two peripheral chip selects in master mode