Freescale Semiconductor MCF5480 - Manual (Page 69)

MCF548x Family Features
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 1-11
frequency from 33–66 MHz. The Flexbus is targeted to support external Flash memories, boot ROMs,
gate-array logic, or other simple target interfaces. Up to six chip selects are supported by the FlexBus.
Possible combinations of address and data bits are the following:
• Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over
PCI bus–PCI not usable)
• Multiplexed 32-bit address and 32-bit data (PCI usable)
• Multiplexed 32-bit address and 16-bit data
• Multiplexed 32-bit address and 8-bit data
The non-multiplexed 32-bit address and 32-bit data mode is determined at chip reset. For all other modes,
the full 32-bit address is driven during the address phase. The number of bytes used for data are determined
on a chip select by chip select basis.
1.4.10 Security Encryption Controller (SEC)
As consumers and businesses continue to embrace the Internet, the need for secure point-to-point
communications across what is an entirely insecure network has been met by the development of a range
of standard protocols. Computer cryptography fundamentally involves calculations with very large
numbers. Personal computers have sufficient processing power to implement these algorithms entirely in
software. When placed upon the embedded devices typically used for routing and remote access functions,
this same computational burden can potentially decrease the throughput of a 100 Mbps Ethernet interface
down to 10 Mbps.
Hardware acceleration of common cryptography algorithms is the solution to the computational bandwidth
requirements of Internet security standards. Discrete solutions currently address this problem, but the next
logical step is to integrate a cryptography accelerator on an embedded processor, such as the MCF548x
family.
Freescale has developed the SEC on the MCF548x family for this purpose. This block accelerates the core
cryptography algorithms that underlie standard Internet security protocols like SSL/TLS, IPSec, IKE, and
WTLS/WAP.
• The SEC includes execution units for the following:
— DES/3DES block cipher
— AES block cipher
— RC4 stream cipher
— MD5/SHA-1/SHA-256/HMAC hashing
— Random number generator compliant with FIPS 140-1 standards for randomness and
non-determinism
• Dual-channel architecture permits single-pass encryption and authentication
1.4.11 System Integration Unit (SIU)
1.4.11.1 Timers
The MCF548x family integrates several timer functions required by most embedded systems. Two internal
32-bit slice timers create short cycle periodic interrupts, typically utilized for RTOS scheduling and alarm
functionality. A watchdog timer resets the processor if not regularly serviced, catching software hang-ups.
Four 32-bit general purpose timers can perform input capture, output compare, and PWM functionality.