Freescale Semiconductor MCF5480 - Manual (Page 716)

MCF548x Reference Manual, Rev. 3
23-8 Freescale Semiconductor
23.4.3.1 External Test Instruction (EXTEST)
The EXTEST instruction selects the boundary scan register. It forces all output pins and bidirectional pins
configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the
boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and
establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to
force a predictable internal state while performing external boundary scan operations.
23.4.3.2 IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the
TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and
other part identification data. The shift register LSB is forced to logic 1 on the rising edge of TCK
following entry into the capture-DR state.Therefore, the first bit to be shifted out after selecting the
IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising
edge of TCK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a
TAP reset, the IDCODE register is selected automatically.
23.4.3.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
• SAMPLE —obtain a sample of the system data and control signals present at the MCU input pins
and just before the boundary scan cell at the output pins. This sampling occurs on the rising edge
of TCK in the capture-DR state when the IR contains the $2 opcode. The sampled data is accessible
by shifting it through the boundary scan register to the TDO output by using the shift-DR state.
Both the data capture and the shift operation are transparent to system operation.
NOTE
External synchronization is required to achieve meaningful results because
there is no internal synchronization between TCK and the system clock.
• PRELOAD—initialize the boundary scan register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in
initialization data. The update-DR state and the falling edge of TCK can then transfer this data to
the update cells. The data is applied to the external output pins by the EXTEST or CLAMP
instruction.
CLAMP 011111 Selects bypass while applying fixed values to output pins and
asserting functional reset
HIGHZ 111101 Selects bypass register while tri-stating all output pins and asserting
functional reset
ENABLE 000010 Selects TEST_CTRL register
BYPASS 111111 Selects bypass register for data operations
Table 23-5. JTAG Instructions (Continued)
Instructio
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IR[5:0] Instruction Summary