Freescale Semiconductor MCF5480 - Manual (Page 717)

Initialization/Application Information
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 23-9
23.4.3.4 ENABLE_TEST_CTRL Instruction
The ENABLE_TEST_CTRL instruction selects a 3-bit shift register (TEST_CTRL) for connection as a
shift path between the TDI and TDO pin. When the user transitions the TAP controller to the UPDATE_DR
state, the register transfers its value to a parallel hold register. It allows the control chip to test functions
independent of the JTAG TAP controller state.
23.4.3.5 HIGHZ Instruction
The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board testing.
HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass register. HIGHZ
also asserts internal reset for the MCU system logic to force a predictable internal state.
23.4.3.6 CLAMP Instruction
The CLAMP instruction selects the bypass register and asserts internal reset while simultaneously forcing
all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held
in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall shift path
to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary
scan register.
23.4.3.7 BYPASS Instruction
The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI
pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device
other than the ColdFire processor is the device under test on a board design with multiple chips on the
overall boundary scan chain. The shift register LSB is forced to logic 0 on the rising edge of TCK after
entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is
always logic 0. This differentiates parts that support an IDCODE register from parts that support only the
bypass register.
23.5 Initialization/Application Information
23.5.1 Restrictions
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive
configurations in which MCU output drivers are enabled into actively driven networks.
23.5.2 Nonscan Chain Operation
Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent
to the system logic. It is recommended that TMS, TDI, TCK, and TRST be pulled up. TRST could be
connected to ground. However, since there is a pull-up on TRST, some amount of current results. The
internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without
asserting TRST.