Freescale Semiconductor MCF5480 - Manual (Page 733)

Memory Map/Register Definitions
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 24-13
24.3.3.11 Initiator Mux Control Register (IMCR)
The DMA supports up to 32 simultaneous DMA request sources, or initiators. For systems where the
number of initiators can exceed 32, it is possible to mux them such that there is user control of which 32
are active at any time. Because there are more than 32 possible DMA initiators on the MCF548x, some of
the initiators are multiplexed to provide software control of which 32 are active at any time. Figure 24-13
shows how the assignments are made from a particular request device to its request number. Sixteen
initiators are always valid, and up to 64 initiators have muxing options for the other 16 request slots. A
single initiator can have multiple muxing options, but only one path should be enabled at a time.
Table 24-10. PRIOR Field Descriptions
Bits Name Description
7 HLD Keep current priority of initiator. This bit can be set or cleared by the programmer at any time. This
bit allows the current initiator to hold priority until the initiator has negated or the task has finished.
When this bit is cleared, an initiator with a higher priority will block the current initiator and force
arbitration. At system reset, this bit is cleared.
0 Allow higher priority initiator to block current initiator
1 Hold current initiator priority level
Note: Setting this bit in task priority allows a low priority task which is currently executing to
complete before allowing a higher priority task to be executed and therefore may not be desirable.
6–3 — Reserved.
2–0 PRI Priority level. These bits are set by the programmer at any time. The PRI field controls the service
priority of tasks by assigning each task a priority level. The highest priority level is 7 and the lowest
priority level is 0. If more than one task/ initiator contains the same priority then the higher numbered
task will take precedence.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Initiator Mux Control
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x805C
Figure 24-12. Initiator Mux Control Register (IMCR)
Figure 24-13. Initiator Assignments
Request
Number (of
Source)
Initiator Mux
Control
Register Bit
Encoding
00 01 10 11
0 none ALWAYS (This initiator is always asserted)
1 none DSPI RxFIFO
2 none DSPI TxFIFO
3 none DREQ0
4 none PSC0 Rx
5 none PSC0 Tx