Freescale Semiconductor MCF5480 - Manual (Page 742)

MCF548x Reference Manual, Rev. 3
24-22 Freescale Semiconductor
24.4 Functional Description
The DMA controller processes microcode tasks that are stored in memory. A task is a sequence of
instructions, referred to as descriptors, that specifies a series of data movements or manipulations. The
DMA controller steps through the descriptors and executes the specified function in a similar fashion to a
CPU executing a program. The data flow for each task can be controlled through signals called initiators
(or requestors) which can be asserted by peripherals, timers, or off-chip devices. While data is being
transferred, it may be manipulated to offload processing from the CPU. Since the DMA controller can only
execute one task at a time, there are priority mechanisms which allow software to control what tasks are
more important to execute when multiple tasks are ready. Interrupts can be generated at various points or
not at all, which is determined by the task descriptors.
The following sections describe various aspects of the operation of the multichannel DMA.
24.4.1 Tasks
A task or task descriptor table is a microcode program that embodies a desired function. An example could
be to gather an Ethernet frame, store it in memory, and interrupt the processor when done. The
multichannel DMA supports 16 simultaneously enabled tasks (one task per channel). By dynamically
swapping task pointers in the task table, an unlimited number of tasks can be supported.
Table 24-19. EREQCTRL Field Descriptions
Bits Name Description
31–8 — Reserved, should be cleared.
7–6 MD Mode. This field set the mode of operation of the external request input. This bits are reset to zero.
00 Idle
01 Level Request
10 Edge Request
11 Piped Request
5–4 BSEL Bus Select. This field selects which of the internal buses to make the compare against. These bits
are reset to zero.
00 System SRAM or external memory write
01 System SRAM or external memory read
10 Internal peripheral write
11 Internal peripheral read
3–2 DACKWID External DMA Acknowledge Width. This field selects the width of the output acknowledge pulse.
The width control is only used in the level and edge request modes. These bits are reset to zero.
00 One clock
01 Two clocks
10 Three clocks
11 Four clocks
1 SYNC Sync. This bit selects the type of timing used by the external request input signal. This control bit
is only used in the level and edge request modes. The piped request mode is always synchronous.
This bit is reset to zero.
0 Asynchronous input timing
1 Synchronous input timing
0 EN Enable. This bit enables the external request/acknowledge function. This bit is reset to zero.
0 Disabled
1 Enabled