Freescale Semiconductor MCF5480 - Manual (Page 743)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 24-23
The details of creating task code is beyond the scope of this document. An API containing pregenerated
task code is provided and described in the “Multichannel DMA API User’s Guide”.
24.4.2 Descriptors
The DMA controller interprets a series of descriptors that specifies a sequence of data movements and
manipulations. A collection of these descriptors is much like a program. The two types of descriptors are
loop control descriptors (LCDs) and data routing descriptors (DRDs). These descriptors allow a “for” loop
programming style for the master DMA engine (MDE). The LCDs specify the index variables (memory
pointers, byte counters, etc.) along with the termination and increment values, while the DRDs specify the
nature of the operation to perform. The MDE allows up to seven levels of nested loops.
The MDE models the following features familiar from most programming languages:
• “For” loops
• Source variables
• Loop-index variables
• Pointers for various uses
• Address offsets for access to structure members
• Multiplication, addition, and logic functions on data
The flexibility of these descriptors allows coding of a broad range of applications, including the following:
• Simple transfers from peripheral to memory, memory to peripheral, or memory to memory
• Computation of checksums, including CRC and internet checksum, while transferring data
• Scatter-gather processing via the indirection capability
24.4.3 Task Initialization
When a task is first enabled, it has a temporary priority which is determined by the state of the
High-priority Task Enable bit of the task’s Task Control register. If that bit is high, then any currently
running task will be swapped out and the MDE will begin parsing the task descriptor table of the task
which has just been enabled. Descriptors are parsed up to the first data routing descriptor (DRD). At that
point, the MDE uses the priority level of the task to determine if it will continue running the task which
has just been enabled or if it will swap in a higher priority task. When using initiator priority, a task has
the priority of the initiator on which it is waiting, which is determined by the current DRD it is executing.
Since tasks can be comprised of many different DRDs, the priority of a task can change throughout the
task when using initiator priority. When using task priority, the task has the priority assigned to it in the
priority register throughout the execution of the task.
24.4.4 Initiators
The multichannel DMA responds to requests from a number of sources, called “initiators.” Many initiators
are derived from FIFO threshold levels to indicate a presence of received data or an empty or near-empty
transmitter.
Other initiators can be timer outputs or custom coprocessors such as the SEC. A timer used as an initiator
can provide bandwidth control for memory-to-memory transfers. A coprocessor initiator could indicate the
completion of some algorithmic processing, whereupon data could be read from the coprocessor. See the
description of the Initiator Mux Control Register for a more complete description of available initiators.