Freescale Semiconductor MCF5480 - Manual (Page 744)

MCF548x Reference Manual, Rev. 3
24-24 Freescale Semiconductor
24.4.5 Prioritization
The multichannel DMA has two basic prioritization schemes to decide which task should run when more
than one is enabled and its initiator is asserted. These are initiator priority and task priority.
When in initiator priority mode, the task with the highest priority active initiator is selected for execution.
There are eight priority levels (0-7). As described, each initiator is associated with a specific task number
(0-15), and that task is executed until the initiator is negated or the loop completes. A task can be
interrupted by a higher priority initiator at loop iteration boundaries and between DRDs.
When in task priority mode, the task with the highest task level priority and an active initiator is selected
for execution. There are eight priority levels (0-7). The highest priority task is executed until the initiator
is negated or the loop completes. A task can be interrupted by a higher priority task at loop iteration
boundaries and between DRDs.
If there are multiple tasks with the same priority level, the highest numbered task is selected for execution.
The priority mode is selected by bit 15 of the PTD Control register. When set to a logic zero, initiator
priority is selected. When set to a logic one, task priority is selected. This bit is set to a logic zero by reset.
24.4.6 Context Switch
Before execution of each DRD, the priority of the active task is compared with other active initiators. If
the active task is still the highest priority, it remains active. Otherwise, it is “swapped out” (context save),
and the task associated with the highest priority initiator is “swapped in” (context restore).
24.4.7 Data Movement
By the time a data routing descriptor has been parsed, between several and all of the memory pointers and
byte counters have been established by the preceding LCDs. When parsing is complete, the MDE begins
acting much like a conventional DMA engine, except that the multichannel DMA can support many data
movements per iteration. It fetches operands and performs operations in the order specified by the DRDs.
Only one memory write per DRD is allowed, but multiple DRDs may be programmed within an LCD. Data
sources or destinations can reside in any addressable storage, including:
• Peripheral FIFOs (comm bus)
• System SRAM
• XL bus space, which provides a path to any external resources including DRAM.
• External memory
NOTE
The DMA cannot access the processor local SRAM.
The data movement engine, or address/data sequencer (ADS, described in Section 24.1.2.2, “Address and
Data Sequencer (ADS) ,”) has an internal register structure that allows it to execute up to four simple nested
loops without any descriptor parsing intervention. This facilitates high performance processing of
algorithms that have small loop counts, but are highly nested, such as image processing filters.
24.4.8 Data Manipulation
The multichannel DMA contains an execution unit, the LURC, which can be used to manipulate data while
it is being transferred. It can be used while transferring I/O data and also to perform logical operations that
allow for descision making within task code. The operation codes for the execution units are stored in the