Freescale Semiconductor MCF5480 - Manual (Page 747)

Programming Model
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 24-27
24.4.10 Termination of Loop
While executing an inner loop, there are two ways to terminate that loop:
1. Loop-termination conditions have been met. A loop is allowed one termination condition. For
example, this could be a byte count for a number of taps in a filter application.
2. The FIFO indicates the end of a full “packet” of information. This response could come from
intelligent peripherals which can recognize frame boundaries in a supported protocol, such as an
Ethernet controller. In these cases, the programmer may not know how many bytes will arrive, so
the “Done” indicator from the peripheral terminates the transfer. A byte counter variable can
indicate the actual number of bytes received.
When a loop terminates (and assuming the initiator is valid), the ADS proceeds to execute any remaining
DRDs that have already been parsed, such as the case where the inner loop is nested inside another loop.
When execution completes, the MDE proceeds to parse any remaining descriptors in the task. If the
appropriate initiator for the next DRD is not asserted, the MDE will perform a context save, followed by
a context restore or parse of the new highest-priority task.
In addition to loop termination, transfer of data can be suspended if the initiator deasserts or if a higher
priority task needs to be swapped into execution.
24.4.11 Interrupts
Interrupts to the processor are allowed on a per-LCD basis, so the processor may be interrupted at the
completion of a loop, or at the end of a task, or not at all. Interrupts may also be masked while allowing
the processor to execute a polling routine.
24.4.12 Debug Unit
The debug module allows software to halt DMA execution based on a several different input conditions.
It compares the value of the Debug Comparator registers to various current aspects of the DMA such as
the address being written, the address being read, the task number, the current pointer and so on. What the
debug module compares the value in the Debug Comparator registers with is dependent on the value of the
Debug Control register. If one of the conditions is met, the debug module will halt the DMA.
24.5 Programming Model
The multichannel DMA requires registers and task memory to be initialized before it will operate.
24.5.1 Register Initialization
This section describes which registers need to initialized either during system configuration time or
potentially each time a task is executed.
1. TaskBAR - The first step in preparing the multichannel DMA is instantiating the task table in a
location in modifiable memory. This table is pointed to by the task base address register
(TaskBAR). This table will be used by the MDE to locate the microcode for each specific task. This
will typically only be set during initialization.
2. PTD Control register - The PTD control register defines global operation options of the DMA,
those which apply to all tasks. This will typically only be set during initialization.
3. DMA Interrupt Mask register