Freescale Semiconductor MCF5480 - Manual (Page 759)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 25-7
25.3 Functional Description
25.3.1 Variable Timer in Baud Clock Generator Mode
In baud clock generator mode, the functionality is the same for both fixed and variable timer channels. The
only difference is the variable timer channel has a 24-bit reference value, and the fixed channel timer only
has a 16-bit reference value.
The following equation can be used to calculate the period of the timer output:
Time-out period = (1/CTCRn[S])
× (CTCRn[CRV])
The duty cycle of the output clock is defined by CTCRn[PCT].
For example, programming the CTCR for one of the fixed channels to 0x0100_0002 will create a 50% duty
cycle output clock at half of the system clock frequency.
25.3.2 Fixed Timer in Initiator Mode
In initiator mode, the fixed timer channel can be used to create a bandwidth control initiator request signal
to the DMA. A cAcknowledge signal from the DMA is an input to the timer to indicate that the requested
task is executing. When the cAcknowledge signal asserts it activates a percent timer, thereby counting the
number of cycles the associated DMA task is active within the period. When the percent timer reaches its
timeout, the timer’s initiator output is negated so that the DMA task will not be serviced again during the
remainder of the timer period.
The fixed timeout period for the counter is determined using the same calculation used for the baud rate
generator mode:
Time-out period = (1/CTCRn[S]) x (CTCRn[CRV])
The percent counter is used to determine the number of clocks that the cAcknowledge signal from the DMA
can be asserted within the period before cInitiator is negated. Once the initiator negates, the task will stop
executing when it reaches the next boundary and will not resume until after cInitiator is asserted again at
the start of the next timer period.
The fixed timer channel can also be programmed to generate an interrupt request if the percent timer does
not timeout by the end of the timer period. The interrupt indicates that there is not enough DMA bandwidth
available for the associated task.
25.3.2.1 Fixed Timer in Initiator Mode Example
Figure 25-6 shows the initiator output generated by a fixed timer channel in initiator mode. For this
example the CTCR is programmed to 0x00A0_0010. This puts the timer in initiator mode with a timeout
period of 16 clocks and a high percentage of 25% (4 clocks).
In the first clock cycle the period counter begins to count, and the cInitiator signal is asserted. At the rising
edge of the clock in cycle 3 the cAcknowledge signal is asserted for the first time and the percent counter
begins to count.
At the rising edge of clock 5 the cAcknowledge signal is deasserted, and the percent counter stops counting
and retains a value of 0x2. The cInitiator signal remains asserted because the percent counter has not
timed out, and the period has not ended.
At the rising edge of the clock in cycle 9 the cAcknowledge signal is asserted for the second time, and the
percent counter begins to count again. At the rising edge of the clock in cycle 10 the cAcknowledge signal