Freescale Semiconductor MCF5480 - Manual (Page 760)

MCF548x Reference Manual, Rev. 3
25-8 Freescale Semiconductor
is deasserted, and the percent counter stops counting and retains a value of 0x3. As before the cInitiator
signal remains asserted because the percent counter has not timed out.
At the rising edge of the clock in cycle 13 the cAcknowledge signal is asserted for the third time, and the
percent counter begins to count. At the rising edge of the clock in cycle 14 the cAcknowledge signal is
deasserted, and the percent counter stops counting and retains a value of 0x4. At this time, the percent
counter has timed out. Consequently, the cInitiator signal is deasserted on the following clock. It will
remain deasserted until the beginning of the next period.
The next period begins at the rising edge of the clock in cycle 17. At that time both counters are reset to
their starting values and the cInitiator signal is asserted. At the rising edge of clock 30 the cAcknowledge
signal is asserted and remains asserted until the rising edge of clock 33. During this time the percent
counter is counting up towards its reference value.
At the rising edge of clock 32 the period counter times out while the percent counter has not reached its
reference value and is still counting. This signifies that the DMA has not been able to provide the specified
bandwidth for the selected task, and the timer interrupt signal is asserted.
At the rising edge of clock cycle 33 a new period begins. Both counters are reset; the cInitiator signal
remains asserted, and the timer interrupt is deasserted. At the rising edge of the clock in cycle 35 the
cAcknowledge is asserted and remains asserted until cycle 39. During that time, the percent counter is
counting up and times out. When it times out at the rising edge in cycle 39, the initiator deasserts on the
next clock edge. The period counter continues to count, and the periods continue on as before.
Figure 25-6. Fixed Timer Channel in Task Initiator Mode
25.3.3 Variable Timer in Initiator Mode
The variable timer channels can also be used to create bandwidth control initiator request signals for the
DMA. The functionality is similar to the fixed channel in initiator mode. The functionality varies in two
ways. First of all, the variable timer channel does not generate interrupts. Secondly, the period counter will
not start until the first time the cAcknowledge signal asserts. This means that the timer has a baseline period
(defined by the CTCR[S] and CTCR[CRV] fields), but the actual period can be greater.
25.3.3.1 Variable Timer in Initiator Mode Example
outputFor this example the CTCR is programmed to 0x00A0_0008. This puts the timer in initiator mode
with a timeout period of 8 clocks and a high percentage of 25% (2 clocks).
Unlike the fixed timer channel, the variable timer channel only has the percent counter and it does not start
counting at this point, it waits for the cAcknowledge signal to enable it.
Period
Counter Value
cAcknowledge
3 4 5 6 7 8 9 a b c d e f 10 1 2 3 4 5
CLK
6 7 8 9 a b c d e f 10 1 2 3 4 5 6 7 8 9 2
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Timer Interrupt
Percent
Counter Value
cInitiator
1
000004 3 2 1 1 2 000000 000004 000003 000002 1 000000 000000
a
1