Freescale Semiconductor MCF5480 - Manual (Page 787)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-25
26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn)
26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn)
This register sets the baud rate in MIR mode.
1 ABORT In most modes this bit is reserved.
In MIR and FIR mode, this bit signifies abort output.
0 Stop sending abort sequence.
1 While the transmitter is sending data or CRC, writing 1 to this bit causes the transmitter
immediately start to output abort sequence (2 or more illegal symbol “0000” in FIR mode, or 7 or
more consecutive in MIR mode). Before the next frame is transmitted, this bit must be reset.
0 NXTEOF In most modes this bit is reserved.
In MIR and FIR mode, this bit signifies next is the last byte.
0 The next write data is not the last byte in a frame.
1 The next write data is the last byte in the current frame. When the processor performs a write to
the TB, an EOF mark is added to the data in the TxFIFO memory. This bit is cleared after writing
to the transmit buffer. This bit is usually set by IP-bus write operation. Since the comm bus has
the transmit_frame_done_b signal, this bit need not be set by the comm bus write operation.
Table 26-24. PSCIRSDRn Field Descriptions
Bits Name Descriptions
7–0 IRSTIM Applies only in SIR mode; in all other modes, this field is reserved.
In SIR mode, this field signifies the timer counter value for 1.6
υs pulse.
In SIR mode, this is used to make 1.6 us pulse when SPUL in the IRCR1 is high and SIPREQ in the
IRCR2 is high. This value should be set so that system clock period * IRSTIM = 1.6
µs
The default value is 54 (decimal) and this is for the 33-MHz bus clock.
Table 26-23. PSCIRCR2n Field Descriptions (Continued)
Bits Name Descriptions