Freescale Semiconductor MCF5480 User Manual
Page 795
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
26-33
provided through a port to the FIFO controller. The read pointer can be both read and written. This ability
facilitates the debug of the FIFO controller and peripheral drivers.
26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn)
The write pointer is a FIFO-maintained pointer that points to the next FIFO location to be written. The
physical address of this FIFO location is actually the sum of the write pointer and the FIFO base, which is
provided through a port to the FIFO controller. The write pointer can be both read and written. This ability
facilitates the debug of the FIFO controller and peripheral drivers. The write pointer is reset to zero, and
non-functional bits of this pointer will always remain zero.
26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn)
The last read frame pointer (LRFP) is a FIFO-maintained pointer that indicates the location of the start of
the most recently read frame. The LRFP updates on FIFO read data accesses to a frame boundary. The
LRFP can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates
which point to begin retransmission of the data frame. The LRFP carries validity information, however,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
READ
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8672 (PSCRFRP0); 0x8772 (PSCRFRP1); 0x8872 (PSCRFRP2) ; 0x8972 (PSCRFRP3)
and MBAR + 0x8692 (PSCTFRP0); 0x8792 (PSCTFRP1); 0x8892 (PSCTFRP2); 0x8992 (PSCTFRP3)
Figure 26-23. RxFIFO (PSCRFRPn) and TxFIFO (PSCTFRPn) Read Pointer
Table 26-33. PSCRFRPn and PSCTFRPn Field Descriptions
Bits
Name
Description
15–9
—
Reserved, should be cleared.
8–0
READ
Read pointer. This pointer indicates the next location to be read by the FIFO controller.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
WRITE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8676 (PSCRFWP0); 0x8776 (PSCRFWP1); 0x8876 (PSCRFWP2) ; 0x8976 (PSCRFWP3)
and MBAR + 0x8696 (PSCTFWP0); 0x8796 (PSCTFWP1); 0x8896 (PSCTFWP2); 0x8996 (PSCTFWP3)
Figure 26-24. RxFIFO (PSCRFWPn) and TxFIFO (PSCTFWPn) Write Pointer
Table 26-34. PSCRFWPn / PSCTFWPn Field Descriptions
Bits
Name
Description
15–9
—
Reserved, should be cleared.
8–0
WRITE
Write pointer. This pointer indicates the next location to be written by the FIFO controller.