Freescale Semiconductor MCF5480 - Manual (Page 799)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-37
A/D bit is set or as a data character if the A/D bit is cleared. The polarity of the A/D bit is selected by
programming bit 2 of PSCMR1. PSCMR1 should be programmed before enabling the transmitter and
loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it
is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the
receiver holding register FIFO stack provided the received A/D bit is a 1 (address tag). The character is
discarded if the received A/D bit is a 0 (data tag). If the receiver is enabled, all received characters are
transferred to the CPU via the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the
status portion of the stack normally used for a parity error (PSCSR bit 5). Framing error, overrun error, and
break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither
calculated nor checked. Messages in this mode may still contain error detection and correction
information. One way to provide error detection, if 8-bit characters are not required, is to use software to
calculate parity and append it to the 5-, 6-, or 7-bit character.
26.4.3 Modem8 Mode
Figure 26-30 shows an example waveform in 8-bit modem mode.