Freescale Semiconductor MCF5480 User Manual
Page 831
Memory Map and Registers
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
27-13
27.6.5
DSPI DMA/Interrupt Request Select Register (DIRSR)
The DIRSR serves two purposes. It enables flag bits in the DSR to generate DMA requests or interrupt
requests. The DIRSR also selects the type of request to be generated. See the individual bit descriptions
for information on the types of requests supported. The user must not write to the DIRSR while the DSPI
is in the running state.
15–12
TXCTR
Transmit FIFO counter. The TXCTR field indicates the number of valid entries in the Tx
FIFO. The TXCTR is incremented every time the DRFR is written. The TXCTR is
decremented every time an SPI command is executed and the SPI data is transferred to
the shift register.
11–8
TXPTR
Transmit next pointer. The TXPTR field indicates which Tx FIFO entry will be transmitted
during the next transfer. The TXPTR field is updated every time SPI data is transferred from
the Tx FIFO to the shift register. See
Section 27.7.2.4, “Tx FIFO Buffering Mechanism
” for
more details. Values are the following:
0000 DTFDR0
0001 DTFDR1
0010 DTFDR2
0011 DTFDR3
7–4
RXCTR
Receive FIFO counter. The RXCTR field indicates the number of entries in the Rx FIFO.
The RXCTR is decremented every time the DRFR is read. The RXCTR is incremented
every time data is transferred from the shift register to the Rx FIFO.
3–0
RXPTR
Receive next pointer. The RXPTR field contains a pointer to the Rx FIFO entry that will be
returned when the DRFR is read. The RXPTR is updated when the DRFR is read. See
Section 27.7.2.5, “Rx FIFO Buffering Mechanism
” for more details. Values are the
following:
0000 DRFDR0
0001 DRFDR1
0010 DRFDR2
0011 DRFDR3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R TCFE
0
0
EOQFE TFUFE
0
TFFFE TFFFS
0
0
0
0
RFOFE
0
RFDFE RFDFS
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8A30
Figure 27-6. DSPI DMA/Interrupt Request Select Register (DIRSR)
Table 27-9. DSR Field Descriptions (Continued)
Bits
Name
Description