Freescale Semiconductor MCF5480 - Manual (Page 839)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-21
for successful communication with an SPI master. These SPI slave mode transfer attributes are set in the
DCTAR0.
27.7.2.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the Tx FIFO or Rx FIFO. The DSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The Tx and Rx FIFOs are
disabled separately. The Tx FIFO is disabled by setting DMCR[DTXF]. The Rx FIFO is disabled by
setting DMCR[DRXF].
The FIFO disable mechanisms are transparent to the user and to host software; transmit data and
commands are written to the DTFR and received data is read from the DRFR.When the Tx FIFO is
disabled, the TFFF, TFUF, and TXCTR fields in DSR behave as if there is a one-entry FIFO, but the
contents of the DTFDR registers and DSR[TXPTR] are undefined. When the Rx FIFO is disabled, the
RFDF, RFOF, and RXCTR fields in the DSR behave as if there is a one-entry FIFO, but the contents of
the DRFDR registers and DSR[RXPTR] are undefined.
27.7.2.4 Tx FIFO Buffering Mechanism
The Tx FIFO functions as a buffer of SPI data and SPI commands for transmission. The Tx FIFO holds
from 1 to 16 longwords, each consisting of a command field and a data field. SPI commands and data are
added to the Tx FIFO by writing to the DTFR. Tx FIFO entries can only be removed from the Tx FIFO by
being shifted out or by flushing the Tx FIFO.
The DSR[TXCTR] field indicates the number of valid entries in the Tx FIFO. The TXCTR is updated
every time the DTFR is written or when SPI data is transferred into the shift register from the Tx FIFO.
The DSR[TXPTR] field indicates which Tx FIFO entry will be transmitted during the next transfer. The
TXPTR contains the positive offset from DTFDR0 in the number of 32-bit registers. For example, TXPTR
equal to two means that the DTFDR2 contains the SPI data and command for the next transfer. The TXPTR
field is incremented every time SPI data is transferred from the Tx FIFO to the shift register.
27.7.2.4.1 Filling the Tx FIFO
Host software or other intelligent blocks can add (push) entries to the Tx FIFO by writing to the DTFR.
When the Tx FIFO is not full, the Tx FIFO fill flag (DSR[TFFF]) is set. The TFFF bit is cleared when Tx
FIFO is full and the DMA controller indicates that a write to DTFR is complete or by host software writing
a ‘1’ to the DSR[TFFF]. The TFFF can generate a DMA request or an interrupt request. See
Section 27.7.6.2, “Transmit FIFO Fill Interrupt or DMA Request ” for details.
The DSPI ignores attempts to push data to a full Tx FIFO, i.e. the state of the Tx FIFO is unchanged. No
error condition is indicated.
27.7.2.4.2 Draining the Tx FIFO
The Tx FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the Tx FIFO to the shift register and shifted out, as long as there are valid entries in the
Tx FIFO. Every time an entry is transferred from the Tx FIFO to the shift register, the Tx FIFO counter is
decremented by one. At the end of a transfer, the DSR[TCF] bit is set to indicate the completion of a
transfer. The Tx FIFO is flushed by setting the DMCR[CTXF] bit.
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI Tx FIFO is empty,
the Tx FIFO underflow flag (DSR[FUF]) is set. See Section 27.7.6.4, “Transmit FIFO Underflow Interrupt
Request ” for details.