Freescale Semiconductor MCF5480 - Manual (Page 850)

MCF548x Reference Manual, Rev. 3
27-32 Freescale Semiconductor
Each condition has a flag bit in the Section 27.6.4, “DSPI Status Register (DSR) ” and a request enable bit
in the Section 27.6.5, “DSPI DMA/Interrupt Request Select Register (DIRSR) .” The Tx FIFO fill flag
(TFFF) and Rx FIFO drain flag (RFDF) generate interrupt requests or DMA requests depending on the
DIRSR[TFFFS] and DIRSR[RFDFS] bits.
27.7.6.1 End of Queue Interrupt Request
The end of queue request indicates that the end of a transmit queue is reached. The end of queue request
is generated when the EOQ bit in the executing SPI command is set and the DIRSR[EOQFE] bit is set.
27.7.6.2 Transmit FIFO Fill Interrupt or DMA Request
The Tx FIFO fill request indicates that the Tx FIFO is not full. The Tx FIFO fill request is generated when
the number of entries in the Tx FIFO is less than the maximum number of possible entries, and the
DIRSR[TFFFE] bit is set. The DIRSR[TFFFS] bit selects whether a DMA request or an interrupt request
is generated.
27.7.6.3 Transfer Complete Interrupt Request
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the DIRSR[TCF_RE] bit is set.
27.7.6.4 Transmit FIFO Underflow Interrupt Request
The Tx FIFO underflow request indicates that an underflow condition in the Tx FIFO has occurred. The
transmit underflow condition is detected only for DSPI blocks operating in slave mode and SPI
configuration. The TFUF bit is set when the Tx FIFO of a DSPI operating in slave mode and SPI
configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while
the DIRSR[TFUFE] bit is set, an interrupt request is generated.
27.7.6.5 Receive FIFO Drain Interrupt or DMA Request
The Rx FIFO drain request indicates that the Rx FIFO is not empty. The Rx FIFO drain request is
generated when the number of entries in the Rx FIFO is not zero, and the DIRSR[RFDFE] bit is set. The
DIRSR[RFDFS] bit selects whether a DMA request or an interrupt request is generated.
27.7.6.6 Receive FIFO Overflow Interrupt Request
The Rx FIFO overflow request indicates that an overflow condition in the Rx FIFO has occurred. An Rx
FIFO overflow request is generated when Rx FIFO and shift register are full and a transfer is initiated. The
DIRSR[RFOFE] bit must be set for the interrupt request to be generated.
Depending on the state of the DMCR[ROOE] bit, the data from the transfer that generated the overflow is
either ignored or shifted into the shift register. If the ROOE bit is set, the incoming data is shifted into the
shift register. If the ROOE bit is negated, the incoming data is ignored.