Freescale Semiconductor MCF5480 - Manual (Page 844)

MCF548x Reference Manual, Rev. 3
27-26 Freescale Semiconductor
Figure 27-15. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
The master initiates the transfer by placing its first data bit on the DSPISOUT pin and asserting the
appropriate peripheral chip select signals to the slave device. The slave responds by placing its first data
bit on its DSPISOUT pin. After the
t
CSC
delay has elapsed, the master outputs the first edge of DSPISCK.
This is the edge used by the master and slave devices to sample the first input data bit on their serial data
input signals. At the second edge of the DSPISCK, the master and slave devices place their second data
bit on their serial data output signals. For the rest of the frame, the master and the slave sample their
DSPISIN pins on the odd-numbered clock edges and change the data on their DSPISOUT pins on the
even-numbered clock edges. After the last clock edge occurs, a delay of
t
ASC
is inserted before the master
negates the CSn signals. A delay of t
DT
is inserted before a new frame transfer can be initiated by the
master.
27.7.4.2 Classic SPI Transfer Format (CPHA = 1)
This transfer format shown in Figure 27-16 is used to communicate with peripheral SPI slave devices that
require the first DSPISCK edge before the first data bit becomes available on the slave DSPISOUT pin. In
this format the master and slave devices change the data on their DSPISOUT pins on the odd-numbered
DSPISCK edges and sample the data on their DSPISIN pins on the even-numbered DSPISCK edges
DSPISCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(CPOL = 0)
DSPICS n/PCSS
t
ASC
DSPISCK
(CPOL = 1)
Master and Slave
Sample
Master DSPISOUT/
Slave DSPISIN
Master DSPISIN/
Slave DSPISOUT
Bit 6
Bit 1 Bit 5
Bit 2 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6 LSB
MSB
MSB
LSB
t
DT
t
CSC
t
CSC
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t
CSC
= PCS to DSPISCK delay
t
ASC
= After DSPISCK delay
t
DT
= Delay after transfer (minimum CS idle time)