Freescale Semiconductor MCF5480 - Manual (Page 845)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-27
Figure 27-16. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
The master initiates the transfer by asserting the CSn signal to the slave. After the
t
CSC
delay has elapsed,
the master generates the first DSPISCK edge and, at the same time, places valid data on the master
DSPISOUT pin. The slave responds to the first DSPISCK edge by placing its first data bit on its slave
DSPISOUT pin.
At the second edge of the DSPISCK, the master and slave sample their DSPISIN pins. For the rest of the
frame, the master and the slave change the data on their DSPISOUT pins on the odd-numbered clock edges
and sample their DSPISIN pins on the even-numbered clock edges. After the last clock edge occurs, a
delay of
t
ASC
is inserted before the master negates the PCSS signal. A delay of t
DT
is inserted before a new
frame transfer can be initiated by the master.
27.7.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
In this modified transfer format, both the master and the slave sample later in the DSPISCK period than in
classic SPI mode to allow for delays in device pads and board traces. These delays become a more
significant fraction of the DSPISCK period as the DSPISCK period decreases with increasing baud rates.
The master and the slave place data on the DSPISOUT pins at the assertion of the CSn signal. After the
CSn to DSPISCK delay has elapsed the first DSPISCK edge is generated. The slave samples the master
DSPISOUT signal on every odd numbered DSPISCK edge. The slave also places new data on the slave
DSPISOUT on every odd numbered clock edge.
The master places its second data bit on the DSPISOUT line one system clock after odd numbered
DSPISCK edge. The point where the master samples the slave DSPISOUT is selected by writing to the
DMCR[SMPL_PT] field lists the number of system clock cycles between the active edge of DSPISCK and
the master sample point. The master sample point can be delayed by one or two system clock cycles.
Figure 27-17 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed master sample points are indicated with a lighter shaded arrow.
DSPISCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(CPOL = 0)
DSPICS n/PCSS
t
ASC
DSPISCK
(CPOL = 1)
Master and Slave
Sample
Master DSPISOUT/
Slave DSPISIN
Master DSPISIN/
Slave DSPISOUT
Bit 6
Bit 1 Bit 5
Bit 2 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6 LSB
MSB
MSB
LSB
t
DT
t
CSC
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t
CSC
= PCSS to DSPISCK delay
t
ASC
= After DSPISCK delay
t
DT
= Delay after transfer (minimum CS negation time)