Freescale Semiconductor MCF5480 - Manual (Page 851)

Initialization and Application Information
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-33
27.8 Initialization and Application Information
27.8.1 How to Change Queues
This section presents an example of how to change queues for the DSPI. The queues are not part of the
DSPI, but the DSPI includes features in support of queue management.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer corresponding to the command word with EOQ set, the EOQ flag
(EOQF) in the DSR is set.
3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,
putting the DSPI in the stopped state. The TXRXS bit is cleared to indicate the stopped state.
4. The DMA will continue to fill the Tx FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel
assigned to Tx FIFO and Rx FIFO. This is done by clearing the corresponding DMA enable
request bits in the DMA Controller.
6. Ensure all received data in the Rx FIFO has been transferred to memory receive queue by reading
the DSR[RXCNT] or by checking DSR[RFDF] after each read operation of the DRFR.
7. Modify DMA descriptor of Tx and Rx channels for new queues.
8. Flush the Tx FIFO by writing a ‘1’ to the DMCR[CLR_TXF] bit. Flush the Rx FIFO by writing a
‘1’ to the DMCR[CLR_RXF] bit.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the
new queue or via CPU writing directly to DTCR[SPI_TCNT] field.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI Tx FIFO and/or setting the corresponding DMA enable request bit for the DMA channel
assigned to the Rx FIFO.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
27.8.2 Baud Rate Settings
Table 27-22 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR
and the baud rate scaler BR in the DCTARn registers. The values calculated assume a 100 MHz system
frequency.